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2009 Microchip Technology Inc.
DS39636D-page 177
PIC18F2X1X/4X1X
16.4.6
MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set, or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
Assert a Start condition on SDA and SCL.
2.
Assert a Repeated Start condition on SDA and
SCL.
3.
Write to the SSPBUF register initiating
transmission of data/address.
4.
Configure the I2C port to receive data.
5.
Generate an Acknowledge condition at the end
of a received byte of data.
6.
Generate a Stop condition on SDA and SCL.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
Start condition
Stop condition
Data transfer byte transmitted/received
Acknowledge transmit
Repeated Start
FIGURE 16-16:
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condi-
tion is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
Read
Write
SSPSR
Start bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb
LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive
Enable
Cloc
kCnt
l
Clock
A
rbit
rat
e/
W
C
O
L
Det
e
ct
(hold
of
fclock
sour
ce)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
Start bit Detect
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